1. Field of the Invention
The present invention relates to a semiconductor memory, and particularly to a semiconductor memory that can store two or more bits of data in each of its memory cells.
2. Description of the Prior Art
A conventional semiconductor memory, for example a flash memory, is constructed and operates as follows. As shown in FIG. 5B, in a flash memory, each of its memory cells is composed of a MOS-type FET (hereafter simply referred to as a transistor) having a floating gate FG (a gate insulated from the surroundings) between a control gate CG and a conducting channel formed between a drain D and a source S within a silicon substrate. To store data, a flash memory exploits the fact that the threshold voltage of this transistor with respect to the control gate varies with the amount of electric charge accumulated in the floating gate. As shown in FIG. 5A, each memory cell is connected to a sense amplifier SA by way of a bit line BL, so that, by detecting the voltage appearing on the bit line BL with the sense amplifier SA, data is read out.
In general, the amount of electric charge accumulated in the floating gate of the transistor is so controlled that, as shown in FIG. 6, the threshold voltage of the transistor falls within one of two states. This makes it possible to store one-bit data, i.e. "0" or "1". That is, one bit of data is stored in each memory cell.
In this case, when a reference voltage, i.e. a voltage approximately in the middle between the two states of the threshold voltage, is applied to the control gate CG of the transistor, if the threshold voltage of the transistor is lower than the reference voltage, meaning that the memory cell is holding "1", the transistor is turned on, and, if the threshold voltage of the transistor is higher than the reference voltage, meaning that the memory cell is holding "0", the transistor is turned off.
While the reference voltage is being applied to the control gate CG, if a constant voltage is applied to or a constant current is supplied to the bit line BL that is connected to the drain D of the transistor, the bit line BL, when the memory cell is holding "1", drops to a low level and, when the memory cell is holding "0", rises to a high level. Thus, the voltage on the bit line varies in accordance with the data stored in the memory cell.
By judging whether the voltage thus appearing on the bit line BL is higher or lower than a predetermined voltage by the use of the sense amplifier SA, data is read out. Specifically, a voltage on the bit line higher than the predetermined voltage represents "0", and a voltage lower than it represents "1".
In recent years, remarkable progress has been made in the techniques for so-called multivalued storage in which two or more bits of data are stored in one memory cell. For example, in four-valued storage, that is, in cases where two bits of data are stored in one memory cell, the amount of electric charge accumulated in the floating gate of the transistor is so controlled that, as shown in FIG. 7, the threshold voltage of the transistor falls within one of four states. This makes it possible to store two-bit data "00", "01", "10", or "11".
To read out data from such a two-bits-per-cell memory cell, it is necessary to prepare, as voltages to be applied to the control gate of the transistor, three reference voltages (hereafter referred to as the first, second, and third reference voltages, respectively) that are approximately in the middle between two adjacent ones of the above-mentioned four states of the threshold voltage.
Specifically, data is read out in the following manner. First, the second reference voltage, i.e. the middle one among the three reference voltages, is applied to the control gate CG of the transistor, and the bit line is operated in the same manner as in the above-described one-bit-per-cell case.
As a result, whether the threshold voltage of the transistor is higher or lower than the second reference voltage, that is, whether the data stored in the memory cell is one of "11" and "01" or one of "10" and "00" is determined.
Next, if the threshold voltage of the transistor has been found to be higher than the second reference voltage, the third reference voltage, i.e. the highest one among the three threshold voltages, is applied to the control gate CG of the transistor, and the bit line BL is operated in the same manner as in the above-described one-bit-per-cell case. On the other hand, if the threshold voltage of the transistor has been found to be lower than the second reference voltage, the first reference voltage, i.e. the lowest one among the three threshold voltages, is applied to the control gate CG of the transistor, and the bit line BL is operated in the same manner as in the above-described one-bit-per-cell case.
As a result, whether the threshold voltage of the transistor is higher than the third reference voltage, between the third and second reference voltages, between the second and first reference voltages, or lower than the first reference voltage, that is, whether the data stored in the memory cell is "00", "10", "01", or "11" is determined.
As described above, to read out data from a two-bits-per-cell memory cell, a read operation needs to be performed in two steps. The greater the number of bits that are stored in one memory cell, the greater the number of steps required to read out data.
Accordingly, a semiconductor memory having multivalued-storage memory cells (of which each can store two or more bits of data) suffers from long access time and high current consumption, and these inconveniences become more serious as the number of bits stored in one memory cell increases.
Moreover, conventional semiconductor memories suffer from reduced data storage accuracy resulting from drain disturbance or read disturbance. Drain disturbance denotes a change in the amount of electric charge accumulated in the floating gate caused by generation and injection of weak hot electrons or a tunnel current resulting from the drain-gate voltage. Read disturbance denotes a change in the amount of electric charge accumulated in the floating gate caused by generation and injection of weak hot electrons resulting from the current that flows through the channel when data is read out.
The change in the amount of electric charge in the floating gate occurs regardless of the number of bits stored in one memory cell. However, semiconductor memories having multivalued-storage memory cells tend to be more susceptible to reduced data storage accuracy, because they have smaller differences between threshold voltages.